Delta-Sigma ADC Basics
Delta-sigma ADCs. Not a new technology by any means, yet still they are regarded by many embedded engineers as mysterious and magical. In this post, I’ll go through the basics of delta-sigma ADCs, and delta-sigma modulation on a higher level.
Understanding delta-sigma ADCs’ benefits compared to different ADCs (SARs, dual slope, etc) will require a broader understanding of delta-sigma modulation and its application in creating an ADC. The block diagram below describes a delta-sigma modulator (DSM) on a high level.
The input signal goes through a subtractor, taking the difference of the input and the output signal (fed through an impulse generator). Remember, this output is a binary density stream! When the output signal is 0, the differences passes the input signal straight through to the integrator. This integrator continues to sum the input until it triggers the compare that follows it (at 0), at which point the output changes from a 0 to Vref. We can think of this as one, for simplicity, but keep in mind that this block diagram is not implementation specific, so 1 may not make sense for every case. When the output signal changes to Vref, the impulse block it passes through causes a very large, negative result from the difference, and thus creates a step down in the integrator’s output, causing the compare result to go to 0 again. All of this can be a little difficult to imagine, so the figure below demonstrates the DSM modulating a DC signal. In theory, the output goes high for an infinitesimally small amount of time, but let’s assume that this is a clocked digital system with a non-infinite impulse function so that we have a useable output.
This difference of sums (delta-sigma, ho-ho!) creates a delta-sigma modulated density stream whose duty cycle is equal to Signal In/Vref. So, if Signal In is 0.5 Vref, we will see a 50% duty cycle delta-sigma modulated density stream at the output.
I can imagine you saying, “OK, that’s cool, but I thought we were talking about delta-sigma ADCs?” We are, though! This delta-sigma modulation is most of the work required to make a delta-sigma ADC. To make this delta-sigma modulator into an ADC, we must simply count the density output and supply a periodic sample pulse to capture the counter’s result and reset it. This relationship is laid out simply in the block diagram below.
This reveals one of the great benefits of the delta-sigma ADC: the process of delta-sigma modulating the input into a density stream and summing it in a counter reduces aliasing of high frequency signals into the pass band greatly. This means the delta-sigma ADC is more resistant to out-of-band noise than other types of ADC.
A practical (simple) implementation of the delta-sigma ADC is implemented below. As we can see, the elements from the basic DSM block diagram are created here in their analog counterparts.
In coming posts, I’ll talk about the benefits and drawbacks of delta-sigma ADCs as compared to other common ADCs (SAR, dual slope, etc.), and also how better, higher order delta-sigma ADCs can be made. Thanks for reading!
